MOS Transistors

• nMOS turns on when gate is high and off when gate is low
  • p-type body with two n-type regions (source and drain)
  • Voltage on “other side” cannot be more than the different between gate and input voltage (drain in a low side configuration)
• pMOS turns on when gate is low and off when gate is high
  • n-type body with two p-type source and drain regions

CMOS Logic Gates

• Two parts:
  • nMOS PDN: connects the output to GND (0) when active
  • pMOS PUN: connects output to VDD (1) when active
• More complex logic functions can be built in a single gate stage by creating series/parallel networks in both the PDN and PUN
  • For more efficient than building the same function from multiple NAND/NOR gates

NOT

NAND

NOR

• nMOS are in parallel to pull the output low when either input is high
• pMOS transistors are in series to pull the output high when both inputs are low

Compound Gates

Example: $!((A \cdot B) + (C\cdot D))$

1. Design the nMOS PDN
   • Pull output down to 0, should turn ON when output should be 0
   • Look at non-inverted version of the function, output is 0 when $(A \cdot B) + (C\cdot D)$ is true
   • AND operations are done by placing transistors in series
   • OR operation is implemented by placing the result of AND operations in parallel
2. Design the pMOS PUN
   • Where the PDN uses series, PUN uses parallel
   • Where the PDN uses parallel, PDN uses series

Pass Transistors & Transmission Gates