<aside> 🐬 Toggle flip flop: built using a DFF. Toggles ints output state (from 0 → 1 or 1 → 9( with each clock pulse if the T input is high. Maintains previous state if T input is 0.

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• Holds previous state
  • When $T$ is kept at 1, it keeps toggling the previous state

Example: Synchronous Binary Up Counter

Input to first TFF is kept constant at 1

State at $Q_0$ (TFF 1) is reversed at every clock tick

Timing Diagram for the Counter

Adding Enable and Reset to Synchronous Counter

input reset_m, clock enable;
output reg[3:0] Q;
always @ (posedge clock, negedge reset_m)
	if(!reset_m)
		Q <= 0;
	else if(enable)
		Q <= Q+1; //4 bits increment by 1

Asynchronous (Ripple) Counter

• $Q_0$ toggle at every clock edge, since input T is 1
• Since $!Q$ drives the clock on the next TFF, there is a small delay, which accumulates
  • Clock only derives first flip flop

Register Enable

• Previously we had an “enable” signal to the counter, which when held high would cause the TFF to toggle
• Here we have a DFF, and since we cannot turn the clock off, we eelct the input to the flip flop via MUX and enable