4.2: Transient Response

Capacitor Charging

• Rate of voltage change depends on the current and capacitance

  $$ I = C \frac{dV}{dt} $$

Key capacitances:

• Diffusion: $C_{db}$ of the driving transistors
• Gate: $C_{gs}$ of the load transistors
• Wire
• Only capacitances connected to the switching node matter — others are ignored

Differential Equation Setup

• For a falling output transition, input steps from 0 → $V_{DD}$, where $I_{dn1}$ is the nMOS transistor current, which depends on the operating region of linear or saturation

  $$ C_{out} \frac{dV_B}{dt} = -I_{dn1} $$

Saturation Region $V_B > V_{DD} - V_t$

$$ \frac{dV_B}{dt} = -\frac{\beta}{C_{out}} \cdot \frac{(V_{DD} - V_t)^2}{2} \quad \text{(Saturation)} $$

Linear Region $V_B < V_{DD} - V_t$

$$ \frac{dV_B}{dt} = -\frac{\beta}{C_{out}} \left(V_{DD} - V_t - \frac{V_B}{2}\right) V_B \quad \text{(Linear)} $$

Practical Limitations

• Inverter ramp response

  

4.3: RC Delay Model

Effective Resistance

• Unit nMOS transistor has effective resistance $R$