RS Latch
NOR RS Latch
NAND SR Latch
Gated RS Latch
With only NAND gates
With NOR and AND gates
Gated D Latch
D Flip-Flops
Transfers input data to the output in synch with a clock signal
IO
D
data input
CLK
:
flip flop response to changes of the D input only at the
edges
of the clock signal (either rising edge 0→1) or falling edge (1→0) translation
