Ep 057: Latch and Flip-Flop Operation

Ep 058: Timing Diagrams of Flip-Flops and Latches

Ep 060: D Flip-Flop Divide-by-Two Circuit

Ep 061: D Flip-Flop Binary Counter/Timer Circuit

Edge Triggered

module Dff(input D, clock, output Q);
	neg Q;
	always @ (posedge clock)
		Q <= D; // assignment used for edged triggered memory (non blocking)
endmodule

Blocking

• Completes and updates LHS before next assignment
• Statements evaluated in the order that they are written
• Used in combinational circuits (no clock)

neg Q1, Q2
always @ (posedge CLK)
	begin
		Q1 = W;
		Q2 = Q1;
	end

Non Blocking

• Values are updated at the end of the always block
  • Statements are evaulated concurrently
• It is used in sequential circuits (where we have a clock)

neg Q1, Q2;
always @ (posedge clock)
	begin
		Q1 <= W;
		Q2 <= Q1;
	end

Dff with clear and preset

• Used when there is a need to return to or go to a known state
  • For instance when we count, we want to start at a known point