Automarker

• For submission: Use the command /cad2/ece241f/public/submit 2 part2.v part3.v
• To check the submission status: Use /cad2/ece241f/public/check submission 2
• A sanity check can be run using /cad2/ece241f/public/2/tester
  • However, it's a basic test to verify file and module names. Complete simulations are still recommended.
• You can test your files by running the following command IN THE SAME DIRECTORY where your files are: /cad2/ece241f/public/2/tester

Part 1

4.1 Verilog File (.v file):

1. Examine mux.v. Understand the structure, especially the two modules mux and mux2to1.
2. Understand the concept of a module and how modules can be instantiated.
3. Recognize how the mux module connects with the pins of the DE1-SoC board.
4. Note the instantiation of the mux2to1 module inside the mux module.

4.2 Simulation File (.do file):

1. Familiarize yourself with the wave.do file and understand its purpose.

   • It sets up the working directory, compiles the Verilog file, and loads the simulation.
   • It also displays signals on the waveform viewer and runs the simulation.

2. Understand how to force values to signals and run the simulation.

   When you “force” a value to a signal, you’re overriding its natural value, forcing it to take on 0 or 1, regardless of what surrounding circuitry might be driving it to

   Running the simulation:

   1. Set up initial conditions by forcing values onto specific signals.
   2. Run the simulation for a specified time.
   3. Observe the circuit's behavior during that time using tools like waveform viewers.
   4. Adjust conditions or inspect results as needed.

3. Action: Open ModelSim, navigate to the directory containing your files, and run the simulation by typing do wave.do.

4.3 Building the Design for FPGA:

1. Run the provided .do file in ModelSim. (This involves ModelSim and the .do file.)
2. Action: Create your own test cases for the .do file. Modify the .do file to apply different inputs (using the force command) and observe the outputs. Validate the behavior of the mux module.
3. Action: Create a new Quartus project for the provided Verilog code (mux.v). Set it up to program the FPGA and test it on your DE1-SoC board. (This involves the .v file, Quartus, and FPGA hardware.)
   • Remember to include the DE1 SoC.qsf file in your Quartus project to correctly map the pins.
4. Compare the output results from the FPGA board with the results from your ModelSim simulations.