L1 - DFF setup time

Output will not flip even though the input flips during a setup time violation

• DFF samples input D on the rising edge of clock, but D has to be stable for some time before the clock edge, so internal latch sees correct value and latches (setup time)
• If D changes too close to the rising edge, internal transmission gate and inverter latch do not have enough time to settle

No clock delay, no setup violation

45.22ns clock delay, no setup violation

45.23ns clock delay, setup violation

$t_{setup} = 231ps$

L2 - DFF $t_{PCQ}$

After DFF captures value on rising edge of clock, output Q does not change instantly

• Takes time for clocked transmission gate to switch, latch nodes to flip, and final inverter to drive the load (clock to Q prop delay)

$t_{pcq} = 428ps$

L3 INV chain + max clock frequency

$t_{inv} = 462ps$

• $t_{setup} = 231ps$
• $t_{pcq} = 428ps$
• $t_{4inv} = 462ps$

Clock period must be greater than PCQ, inverters, and setup delays