TA marking

• Part 1 schematic
• Part 2 code
• Part 2 modelsim

Part 1

1. Draw D latch schmatic with 7400 series chips
2. Build gated D latch using chips and breadboard
   1. Hook up power and ground
3. Study behaviour of latch for different D and Clk settings
   1. Observe when Clk is high and change D
   2. Observe when Clk is low and change D several times
   3. How to set Q high?
   4. How to set Q low?
4. What are all the cases to show its working correctly?

Part 2

• D is value you want to store
• CLK controls when the flip flop samples or stores data
  • Operates on the rising (posedge) or falling (negedge) of the cloc

• Create verilog for ALU circuit
  • Use same wire and instance names in schematic
• Simulate with modelsim
  • Prepare and justify test cases

ModelSim

• 10ns periodic CLK
• Reset to 1 (active) and then deactivates the reset signal
• Edge cases
  • Boundary values (1111)
  • Large left shifts
  • Multiple operations without reset
  • Overflow handling
  • Changing Function and Data