Part 1

Part 2

You are to design a counter that continuously outputs hexadecimal values from 0 through F, with varying speeds based on the Speed input. There is a parameter for clock frequency (CLOCK_FREQUENCY), and you need to account for it in your design.

1. Building the Counter: You can use D-flip flops to construct the counter. In Verilog, this can be abstracted as simply adding 1 to the previous state of the counter.
2. Rate Divider:
   • Purpose: This module is responsible for generating slower pulses (Enable) from the input clock based on the given speed.
   • Implementation:
     • To generate the pulse, count N cycles of your input clock before generating it.
     • The counter should count down to 0 and generate an enable pulse when it reaches 0.
     • Your counter should consider varying clock frequencies and different numbers of clock cycles. This flexibility can be achieved using parameters and conditional loading of the counter's starting value.
3. Display Counter:
   • Purpose: This module takes the pulses (Enable signals) from the RateDivider and uses them to determine whether the counter should change on a given clock pulse.
   • Implementation: Use an enable signal to dictate when a flip flop or counter should change.
4. Integration: Once you've created and tested the RateDivider and DisplayCounter modules individually:
   • Instantiate them in the part2 module.
   • Interconnect them accordingly, ensuring the Enable output of the RateDivider connects to the EnableDC input of the DisplayCounter.
   • Test the combined system and verify its functionality against the requirements.
5. FPGA Testing:
   • For on-board testing, integrate a HEX Decoder module (you can reuse one from a previous lab) to display the counter's output.
   • Ensure the clock frequency is set to 50 MHz for the FPGA test demo.
   • HEX display rotates from 0 to F at certain speeds
6. Schematic: It's important to draw a schematic diagram of your design before writing any code. This diagram should display the entire structure of the part2 module, including both the RateDivider and DisplayCounter modules inside it. Prepare this schematic before the lab session.
7. Testing:
   • It's highly recommended to simulate and test each module (RateDivider and DisplayCounter) separately before integrating them.
   • When simulating, especially for the RateDivider, pay attention to the number of cycles to ensure the Enable pulse operates correctly.

Part 3

1. Morse Code Patterns: The first thing you need to do is to convert the given Morse code representations for the letters A through H into sequences of 0's and 1's. You need sequences of 12-bits for each letter. For instance:
   • A is represented by — which becomes 10 111, and when extended to 12-bits becomes 101110000000.
2. Shift Register: You need a 12-bit shift register. When a letter is selected, you'll load the corresponding 12-bit pattern into this shift register. Every 0.5 seconds, you'll shift out one bit from this register. This bit will be the value for DotDashOut.
3. Rate Divider: To generate the 0.5 seconds pulse, use a rate divider. Count how many clock cycles correspond to 0.5 seconds based on the provided CLOCK FREQUENCY parameter.
4. MUX for Letter Selection: Use a 3-to-8 decoder to decode the 3-bit Letter input into one of the eight possible letters. Use these outputs to select the appropriate Morse code pattern from your 12-bit patterns for each letter.
5. Counters:
   • Use a counter to keep track of how long the DotDashOut signal should be high for.
   • You also need another counter to ensure the entire sequence for a letter takes 6 seconds (since you have 12 bits and each bit lasts 0.5 seconds).
6. NewBitOut Pulse: Generate a pulse for NewBitOut similar to Part 2. Every time a new bit is shifted out, NewBitOut should be set to 1 for one clock cycle.
7. Reset & Start Logic: Implement the logic such that:
   • When Reset is high, everything should be initialized to its default state.
   • When Start is asserted for 1 clock period, the Morse code for the selected letter should start being output.