Part 1

Step 1: Create the Memory Module in Quartus

1. Open Quartus Prime software.
2. Access the IP Catalog under Tools to select the components you need.
3. Choose the RAM:1-PORT option from the Basic Functions under On Chip Memory.
4. Specify the location and name (part1.v) for your Verilog file which will describe the memory module.
5. Configure the memory: Set it to be 4-bits wide and have a depth of 32 words.
6. Choose settings: Memory block type set to Auto, Single Clock configuration, and unselect 'q' as a registered port.
7. Finish the wizard to generate the Verilog file.

Step 2: Simulate the Memory Module

1. Examine the generated Verilog file to ensure it has the correct module with necessary ports as per your schematic.
2. Use ModelSim to simulate the module. Create test benches that check the RAM operation, both reading and writing, as per the timing diagrams you have.
3. Use the simulation to confirm that the RAM operates correctly. Ensure your test cases cover enough scenarios to validate proper functionality.

Step 3: Create Quartus Project for the Top-Level Circuit

1. Create a new project in Quartus for your complete circuit.
2. Create a top-level module that connects the memory module (part1) to the DE1-SoC board interfaces (such as switches, buttons, and HEX displays).
3. Map the part1 ports to the DE1-SoC board pins as shown in your Table 1.
4. Simulate the top-level module with ModelSim to ensure all connections are correct and the system behaves as expected.

Step 4: Compile and Test on FPGA

1. Compile the project in Quartus to generate a bitstream, making sure that there are no synthesis errors.