Topics

• CMOS process and fabrication
• MOS non-idealities (tested)
• CMOS circuit (tested)
• Stick diagrams (tested)
• Parasitic capacitance
• Pass transistor output voltage
• Elmore delay (tested)
• Transistor sizing (worst/best case)
• Transfer characteristics (VIL, VIL, VOL, VOH)
• Pi model (tested)
• Logical effort of paths
• Dynamic power dissipation (tested)
• Static power dissipation
• Static ratioed/pass transistor logic
  • Pseudo nMOS
  • Static CMOS
• Dynamic/domino logic
• Bistability/latches
• Edge triggered storage
• All timing equations/definitions