The Sequential Model

Implicit model of all modern commerical ISAs

• Basic feature: the program counter (PC)
• Defines total order on dynamic instruction
  • Next PC is PC++ unless instruction says otherwise
• Order and named storage define computation
  • Value flows from instruction X to instruction Y via storage A if and only if X names A as its output, and Y comes after X in the total order and Y names A as its input
• Processor logically executes loop at left
  • Instruction execution is assumed to be atomic
  • Instruction X finishes before X+1 starts
• Alternatives proposed:
  • Dataflow

Datapath: Single Cycle

Takes too long to propagate in a single cycle!

• Datapath: functional units (ALU), registers, memory interface (data cahce)
• Control: decode portion
  • Muxes (drawn with ovals)
  • Write enables: regulate the flow of data in the datapath
  • Translate ops into control

Breaking instructions down

• Instruction fetch (F): instruction fetched form memory at address indicated by PC
  • Increment PC to point to next instruction in sequence
• Instruction decode (D)
  • Decode instruction to find type
  • Read registers
• Execution (X)
  • ALU performs arithmetic/logic operation (arithmetic instruction)
  • Computer memory address (load/store instruction)
  • If branch, compute target PC and update
• Memory access (M)
  • Contents of Mem[addr] are fetched (load)
  • Contents of Mem[addr] are modified (store)
• Writeback (W)
  • Write instruction result to register

Datapath: Multi-Cycle

Add latches to create the multicycle implementation!o