Finite State Machine Control

What happens in each clock cycle instruction?

• For any register if it is enabled, then its input must be correct

  • If not enabled, doesn’t matter what the D input is

• For every instruction, we will do “something: during the first clock cycle of its execution

  

• We only need 4 cycles to complete ADD, SUB, and NAND

Cycle 1 - Instruction Fetch (Add)

• The instruction at the memory address pointed to by PC (address of next instruction to be executed) is read [IR] = Mem[PC]
• Instruction Register (IR) loads the fetched instruction from memory (IRload)
• The PC is incremented to point to the next instruction in memory

• IR = Mem[[PC]] - load the instruction register with the contents of the memory location given by the program counter

• Also called Fetch the instruction - do this for all instructions

  [IR] = Mem[[PC]]
  [PC] = [PC] + 1
  

• Clever optimization- had said that PC = PC +1 happens at end, but since we always do this, we can do that at the same time we’re fetching PC → saves time

  • Old value of PC is used in fetch

Cycle 2 - Instruction Decode (Add similar for SUB and NAND)

• Instruction in the IR is decoded to understand what actions are to be taken
  • Register identifies source operands (i.e., RA and RB) are extracted from the instruction
  • Register A = RF[IR7..6] indicates a register file read operation

• Decode: look at the instruction and figure out which it is, so know what to do next

  Register A = RF[[IR7..6]]
  Register B = RF[[IR5..4]]
  

Another clever optimization:

• Many instructions will be wanting to access Ra and Rb if the instruction calls for that
• Get them from the register file while we’re decoding, in case we need them
• In case the hardware is there we can get it to do this now rather than a later cycle
• We might not need it, depending on the instruction

Control signals to activate to do this: