Interrupts in more detail

• Processor can have 32 separate IRQ lines
• Processor knows that the interrupt handler is at address 0x20

5 things must happen to make this work correctly:

1. Know where to go → 0x20
2. Where to return → stored ea register (r29)
3. Don’t mess up stuff like the registers in the main program
4. Enable interrupts in the processor
5. Enable interrupts from the device (i.e., push buttons)

4. Enabling Interrupts from the Processor Side:

There a 4 new registers in Nios II related to this

ctl0: control/status register

Holds flags to indicate the current state of the processor. Enabling interrupts globally in the processor is done by setting the appropriate bit in this register

• Bit 0: Processor Interrupt Enable (PIE)
  • if = 0, no interrupts can happen
  • if = 1, interrupts are allowed (globally)
• Bit 1: User/Supervisor bit
  • If equal to 1, we are in user mode
  • If equal to 0, we are in supervisor mode

Example privilege for supervisor mode:

ctli registers (crtl0, crtl1, …)

• Read Control Register: rdctl
• Write Control Register: wrctl
  • Configuring the processor to respond to interrupts
• Can access registers r24 (et) and r29 (ea)
• To enable the PIE bit in crt0/status register do this (only if in supervisor mode):

movi r8, 0b01 ; PIE bit = 1 (enabled)
                ; U/S = 0 (Supervisor)
wrct1 ctl0, r8 ; crtl0 <- r8

ctl1: estatus