Simple Processor Instructions

NAND Instruction

nand Ra, Rb

• Ra ← $\overline {(Ra \& Rb)}$
• Condition code flag bits Z and N are set

Encoding:

Load Instruction

load Ra, (Rb)

• Ra ← Mem (Rb)
• PC ← PC + 1

Encoding:

Store Instruction

store Ra, (Rb)

• Mem(Rb) ← Ra
• PC ← PC + 1

Encoding:

Conditional Branch

bne r6, r5, loop

• bnz Imm4
  • Branch if Z==0 , since Z = 1 when it is 0
  • Branch target address is the absolute address of where to go to if the condition (Z = 0 here) is true

Encoding:

• Branch target address = PC + SE(Imm4)
  • Sign extend to 8 bits
• Called a relative branch → most computers do it this way
• If Z==0, then PC <- PC + SE(Imm4), else, PC <- PC + 1

loop: 
    load r2, (r0)
    load r3, (r1)
    sub r2, r3
    bnz loop

Shift Instruction

Only a 3 bit opcode

Datapath

Registers

Made out of flip-flops