Midterm Review

See notes

Nios II processor architecture

• Registers r0 → r31
• Special registers: ra, sp, ea

Memory organization

• Byte addressability
• Each individual byte has its own individual address
• Words, half words, or bytes
• Order of bytes within a word by address (little vs big endian)
• Translation of binary into hexadecimal
• Loads and stores to memory (instructions
  • ldw, stw
  • ldb, stb
  • ldh, sth
• Indexed addressing
  • i.e.,ldw r9, (r8) and stw r10(r8)
• Index with offset
  • i.e., ldb r10 3(r9)

Functions of instructions

• mov, movi, movia (just two movi instructions)
• add, addi, sub, subi
• Conditional branch instructions
  • bge r4, r0, loop
• Shift and rotate instructions
  • srl, sll, srli, slli, rol (rotate left)