Audio I/O

• ADC to sample audio and convert to input digital signal
• DE1-SoC uses 24 bits for each value, sampled at 8 KHz
• DAC to interpolate audio and convert to output analog signal

FIFO

Processor not ready to receive all the digital values at once when they arrive every 0.0001s, requires buffering (temporary storage) of data

Specific memory mapped registers for audio interface.

• Microphone → ADC → Input FIFO → Computer → Output FIFO → DA → Speaker
  • Limited by 128 samples on DE1
• Load from the computer to input FIFO memory-mapped address gets the next sample (first out) from the sequence)
• Store to output FIFO places the next output sample on to the output FIFO, which is then, in time, to the DAC

1. control register

Status register at address 0xff203040

• If you store into it you write as a control register
  • Writing a 1 into CR causes input (read) FIFO to be cleared (good to do at the start
  • Writing a 1 into CW clears the output FIFO
• If you read from it, it gives information as a status register
• RI bit goes to 1 as a status if the input?read FIFO is 75% full or more
  • It’s filling up, we need to do something about it
• WI bit goes to 1 if the output/write FIFO is ≤ 25% full
  • Needs more
• RE bit is a control bit
  • If set to 1, then RI bit will cause an interrupt request to the processor
• WE causes an interrupt when WI goes to 1

2. fifospace register

How empty/full the input/output FIFOs are