Cache Memory Design

If a memory location is accessed, it is likely to be accessed again soon by keeping recently accessed data close to the processor

• Processor makes memory access requests to the memory system
• If can keep many of the memory locations that the processor wants to access in the cache, the the memory can satisfy access requests much more quickly
  • A request may ‘hit’ (be present), and ‘miss’ (not be present) in the cache
• Vocabulary terms
  • Cache line
  • Memory block
  • Direct mapped cache
  • Associative cache
  • Write-back cache
  • Write-through cache
  • Tag bits
  • Valid bit
  • Dirty bit

Architecture

Cache is a memory- it has rows and columns

• Each row contains several consecutive main memory words, not just 1
  • Known as a cache “line”
  • Here we will assume every word in the main memory (however big it is) has a different address

Example Cache

4 lines and 4 words/line

• D: Dirty Bit
  • Set to 1 if there is a write to the line
  • Data being dirty means the contents of a cache line hasve been modified after being loaded from main memory, but the new value has not yet been written back into the main memory
• V: Valid Bit
• Main memory is also organized into blocks of words
  • The number of words in a block is as the same as the number of words in a cache line
• For the above cache, the block size of main memory would be 4 words

  • Block size = cache line size

    

Where in the cache can a given main memory block reside?

• If just one specific place, based on the block number, we call that a direct-mapped cache
• If the block is allowed to go into more than one cache line, it is called an associative cache
  • Can go into some or all lines

How do we know if the block (i.e., memory words) that the processor wants to access is already in the cache?

• Use the Tag bits associated with each line to say which main memory block this cache line came from
  • The tag is the main memory block number